The present invention relates to Metal-Oxide Semiconductor (MOS) devices, and more particularly to a low power, three-terminal tunneling MOS device having operational characteristics that are a hybrid between a MOS transistor, a gated diode and a tunneling diode.
A conventional n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) is shown in the cross-sectional diagram of FIG. 1. The MOSFET 10 consists of a source 12 and a drain 14, two highly conducting n-type semiconductor regions that are isolated from the p-type semiconductor substrate 16 by reversed-biased p-n diodes. A gate electrode 18 generally covers the region between source and drain and is separated from the semiconductor by the gate oxide 20.
The applied voltage will determine which n-type region provides the electrons and becomes the source 12, while the other n-type region collects the electrons and becomes the drain 14. The voltages applied to the drain and gate, as well as, to the substrate 16 by way of the back contact 22 are referred to as the source potential.
The voltage applied to the gate electrode 18 controls the flow of electrons from the source 12 to the drain 14. A positive voltage applied to the gate electrode attracts electrons to the interface between the gate oxide 20 and the semiconductor substrate 16. These electrons form a conducting channel between the source and the drain, referred to as the inversion layer 24. As shown the inversion layer 24 is formed adjacent to the gate oxide 20 above the depletion layer 26. Gate current is not required to maintain the inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is that the voltage that is applied to the gate controls the current between drain and source.
FIG. 2 is a plan view diagram of the MOSFET of FIG. 1. The plan view diagram illustrates the gate electrode length L, and the gate electrode width W. Note that the gate electrode length is not defined as the actual physical length of the gate electrode 18, but rather the gate length is defined as the distance between the source region 12 and the drain region 14. The overlap between the gate electrode and the source and drain region is required to ensure that the inversion layer 24 forms a continuous conducting path between the source and drain regions. Typically, this overlap is kept to a minimum in order to minimize parasitic capacitance in the device. In conventional MOSFET devices variances in the length of the gate electrode will affect the turn-on voltage of the device. In this regard, larger gate length devices will require more turn-on voltage and smaller gate length devices will require less turn-on voltage.
Low power electronics based on the style of Complementary Metal Oxide Semiconductors (CMOS) is principally driven by a reduction in the power supply voltage. This is due to the power consumed by a CMOS circuit being primarily due to the charging/discharging of capacitances in the circuit. This power can be defined as P=xc2xdCV2f, where C is the capacitance of the circuit, V is the power supply voltage, and f is the frequency of the circuit. This relationship makes it apparent that the power is dependent on the square of the voltage.
The second factor that is driving down the CMOS power supply is the scaling of the individual transistors, and the resulting reliability and performance constraints on the power supply voltage. The drive current that can be conducted by a MOS transistor is directly related to the power supply voltage, thus simply reducing the voltage, reduces the drive current, which results in a decrease in the speed and hence the performance of the circuit. Scaled devices are designed to maintain the current drive as much as possible.
One of the variables available to the device designer is the threshold voltage (the transition voltage required to turn the device from an off state to an on state) which determines the drive current. Reducing the threshold voltage increases the drive current of the transistor, however, if the threshold voltage is reduced too far, the off-current of the transistor increases. The off-current needs to remain low to minimize the power consumed due to leakage currents and also to enable the circuit to utilize dynamic logic. The off-current will increase for two principle reasons: the sub-threshold slope and the short channel effect. There is a maximum theoretical rate at which a transistor current will decrease as the gate voltage is decreased. This rate is referred to as the sub-threshold slope and it sets a minimum value for the threshold voltage. In addition, as the transistor is scaled down in size, the threshold voltage tends to decrease and the sub-threshold slope worsens. This further increases the minimum value of the designed threshold voltage. Additionally, variations in the processing leads to variations in the gate length of the transistor and hence variations in the threshold voltage. Thus, the transistor must be designed to have a high enough threshold voltage to maintain a minimum off-current for the shortest transistor.
Much of the effort to date in low power electronics has been focused on silicon-on-insulator (SOI) MOS transistors. These devices have steeper sub-threshold slopes due to the thin silicon channels and reduced parasitic capacitances due to the buried insulator film.
In electrical devices fabricated with semiconductor materials an electron tunneling effect can be realized by forming a junction between a highly doped P-type semiconductor material and a highly doped N-type semiconductor material. The junction provides for a negative resistance characteristic, whereby, as the forward voltage across the junction is increased the current through the junction decreases. The negative resistance characteristic has been beneficially implemented in amplifiers, mixers, oscillators, detectors and the like.
The tunneling of electrons at the PN junction occurs most effectively when a high electric field exists in the semiconductor. For example, tunneling can most readily occur within a reverse-biased depletion region of a silicon PN junction. A narrow depletion region can be achieved when the doping level of the P-type and N-type materials is high, typically on the order of about 1E18 atoms per cubic centimeter (cm3) or higher. The narrow depletion region allows for electrons to tunnel from the P side to the N side where otherwise they would not be prone. The phenomenon in which the valence band electrons penetrate through the energy gap into empty conduction band states is termed xe2x80x9ctunnelingxe2x80x9d.
Most tunneling devices, to date, have been two-terminal diode type devices. While the two-terminal devices are advantageous in many applications, such devices are typically required to be integrated with other devices to achieve an overall circuit function. In addition, the two-terminal device does not typically lend itself to controlling the tunneling effect without implementation of external circuits. Thus, a need exists to develop a semiconductor device having tunneling capabilities and more than two terminals to allow for control of the device characteristics. In addition, such a device will benefit from having a smaller gate voltage transition between the off-current and on-current states and which also has less dependence on the lateral dimensions of the device. Additionally, a need exists to develop a semiconductor device that exhibits other beneficial electrical characteristics beyond negative resistance characteristics to thereby enhance the applicability of such devices.
The present invention provides for a three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode.
The semiconductor device of the present invention will include a lightly doped substrate of a first conductivity type. The substrate will typically be formed of a conventional silicon-on-oxide (SOI) substrate although it is also possible to form the device in composite with other similar devices using junctions and/or reverse bias junctions. The lightly doped substrate will include a first heavily doped region of a first conductivity type formed in the substrate and a lightly doped layer of a first conductivity type disposed on the substrate and the first heavily doped region. The lightly doped layer of a first conductivity type will have a predefined thickness, generally a thin layer, to provide for electron tunneling between the conduction band and valence band during device operation.
The semiconductor device of the present invention will also include a gate insulator layer disposed on the lightly doped layer and underlying a portion of the first heavily doped region. A gate electrode is disposed on the gate insulator layer. As such, the device of the present invention vertically aligns the gate electrode, the lightly doped layer of a first conductivity type and the heavily doped region of the first conductivity type. By implementing a lightly doped region, between the gate and the heavily doped region, precise control over the threshold voltage can be realized. In preferred embodiments of the invention the gate insulator layer will comprise a high dielectric constant material, typically in the range of about 25. The high dielectric constant material will increase the capacitive coupling between the gate electrode and the interface surface of the substrate.
The semiconductor device of the present invention will additionally include a second heavily doped region of a first conductivity formed in the substrate extending into the first heavily doped region of a first conductivity. The second heavily doped region of a first conductivity will form either the drain or the source depending upon the conductivity. As such, first heavily doped region of a first conductivity is an extension of either the drain or the source. The device also includes a heavily doped region of a second conductivity formed in the substrate extending into the lightly doped substrate and spatially isolated from the first heavily doped region. The heavily doped region of a second conductivity will form either the source or the drain depending upon the conductivity.
In one specific embodiment of the present invention the semiconductor device includes a SOI substrate having lightly doped P-type silicon disposed on an insulator. A heavily doped P-type region is formed in the silicon. This region serves as a source extension region. A lightly doped P-type layer is disposed on the silicon and the heavily doped P-type region. The lightly doped P-type layer will have a predefined thickness, generally minimal thickness, to provide for electron tunneling between the conduction band and valence band during device operation.
A gate insulator layer is disposed on the lightly doped P-type layer and underlies a portion of the heavily doped P-type region. A gate electrode is disposed on the gate insulator layer. Hence, in vertical alignment a lightly doped P-type region is disposed between the gate and the heavily doped P-type region to allow for precise control over the threshold voltage during device turn-on. The gate insulator layer will comprise a high dielectric constant material, typically in the range of about 25. The high dielectric constant material will increase the capacitive coupling between the gate electrode and the interface surface of the substrate.
The second and third terminals of the device include a P-type source region formed in the silicon adjacent to a first vertical side of the gate insulator layer and gate electrode. The P-type source region extends into the heavily doped P-type region such that the heavily doped P-type region becomes an extension of the source. A N-type drain region is formed in the substrate adjacent to a second vertical side of the gate insulator layer and gate electrode that is opposite the first vertical side, the N-type drain region extending into the lightly doped P-type silicon layer and spatially isolated from the heavily doped region.
Additionally, the present invention is defined by a method for fabricating the semiconductor device of the present invention. An SOI substrate is provided that has a lightly doped silicon layer of a first conductivity type. A first heavily doped region of a first conductivity type is defined within the silicon layer, typically via ion implantation processing. A lightly doped layer of a first conductivity type is disposed on the silicon layer and the first heavily doped region of a first conductivity type. The lightly doped layer of a first conductivity type is typically disposed by low temperature epitaxial growth processing. A gate insulator layer is disposed on the lightly doped layer of a first conductivity type and a gate electrode is then disposed on the gate insulator layer. The gate insulator and gate electrode being defined in an area that underlies a portion of the first heavily doped region of a first conductivity type.
Defining the second and third terminals completes the device fabrication. A second heavily doped region of a first conductivity type is defined in the silicon adjacent to a first vertical side of the gate insulator and gate electrode. The second heavily doped region of a first conductivity type will extend into the first heavily doped region of a first conductivity type. A heavily doped region of a second conductivity type is defined in the silicon adjacent to a second vertical side of the gate insulator and gate electrode, opposite the first vertical side. The heavily doped region of a second conductivity type is spatially isolated from the first and second heavily doped regions of a first conductivity type. The second heavily doped region of a first conductivity type and the heavily doped region of a second conductivity type are typically formed by ion implantation processing.
The present invention provides for a three terminal hybrid semiconductor device. By providing for high doping under the gate electrode the valence and conduction bands are bent sharply during device turn-on with a very thin depletion layer. This band bending brings the conduction band edge at the surface below the valence band edge slightly further into the substrate. When the bands are bent to this degree, and the spatial separation between these points is minimal, electrons can tunnel between the conduction band and valence band. The effect is a sharp increase in tunneling current due to the onset of the energy level overlap of the band edges of the conduction and valence bands and the large density of states within the bands.
Additionally, by providing for a lightly doped region between the gate electrode and the heavily doped region precise control over the threshold voltage can be realized. The vertical stack formation (i.e., gate, lightly doped layer and heavily doped region) of the device of the present invention is not affected by gate length because the tunneling current is determined by the vertical electric field. As a further inventive attribute, the high dielectric constant gate insulator increases the capacitive coupling between the gate electrode and the insulator-to-substrate interface to provide for sharp turn-on voltage.